HSINCHU, Taiwan, R.O.C., July 21 --

- New iDRC and iLVS Data Formats Ensure Data Accuracy and Enable Extensive EDA
Support of Physical Verification Related Applications in TSMC 40nm Process

Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today
unveiled interoperable design rule check (iDRC) and layout-versus-schematic
(iLVS), two unified electronic design automation (EDA) data formats, for TSMC 40
nanometer (nm) process technology.

TSMC iDRC and iLVS formats unify process design rules specification and
technology file generation, simplify data delivery, and ensure data integrity
and interpretation. Physical verification and analysis EDA applications, such as
DRC and LVS tools, which support iDRC and iLVS formats, will be able to receive
accurate design rules data from the iDRC and iLVS files developed and supported
by TSMC. The TSMC iDRC/iLVS initiative is supported by major EDA ecosystem
partners including Cadence, Magma, Mentor, and Synopsys. The first 40nm
iDRC/iLVS was developed in collaboration with TSMC development partners, Mentor
and Synopsys, and QA/validation partners, Magma and Cadence. iDRC and iLVS are
two of several interoperable EDA interface formats co-developed between TSMC and
its design tool partners as part of the TSMC Open Innovation Platform(TM).

Design rules for advanced process technologies are more complex and require
detailed and accurate descriptions for correct chip layout creation and
post-layout analyses. TSMC collaborates extensively with the EDA partners in the
iDRC/iLVS initiative, defines the unified format based on TSMC process
requirements, works with EDA partners to implement the new format support in the
tools, and closes the loop by qualifying tool accuracy against actual silicon
measurements, eliminating data inconsistency, reducing customer tool evaluation
time and improving design accuracy. The qualification result is to be found in
TSMC EDA qualification program on TSMC-Online, the company’s customer
portal. Multiple EDA companies are participating in the qualification program.

TSMC is the first foundry to collaborate with multiple EDA vendors to create
and qualify an interoperable physical verification format that optimizes data
delivery and interpretation between physical verification and analysis tools and
advanced process technologies, said ST Juang, senior director of Design
Infrastructure Marketing at TSMC. iDRC and iLVS are part of the TSMC Open
Innovation Platform that includes the Active Accuracy Assurance Initiative. This
new unified EDA data format provides designers the ability to select qualified
EDA tools to match their design needs, improve compliance with TSMC processes,
and ensure design accuracy for first-time silicon success.


The TSMC iDRC and iLVS files will be available Q3 2009 in limited release and
to selected customers. General release to other customers is targeted for Q4
2009. Customers may access the technology files at the TSMC Online customer
design portal http://online.tsmc.com/online/ or contact their local sales and
support representatives for details.

About TSMC Active Accuracy Assurance Initiative (AAA)

TSMC’s AAA initiative is a broad-based program that encompasses all
design ecosystem components. It provides accurate standards for all TSMC
partners, EDA vendors, IP providers, library developers, and Design Center
Alliance (DCA) members. The standards apply to tools, building blocks, and
technologies, including TSMC Reference Flow, design for manufacturing (DFM)
tools, process design kits (PDK), design support and backend services.

About TSMC Open Innovation Platform(TM)

The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst
the semiconductor design community, its ecosystem partners and TSMC’s IP,
design implementation and DFM capabilities, process technology and backend
services. The Open Innovation Platform includes a set of ecosystem interfaces
and collaborative components initiated and supported by TSMC that efficiently
empowers innovation throughout the supply chain and enables the creation and
sharing of newly created revenue and profitability. TSMC’s AAA initiative
is a critical part of the Open Innovation Platform, providing the accuracy and
quality required by ecosystem interfaces and collaborative components.

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing
the industry’s leading process technology and the foundry’s largest
portfolio of process-proven libraries, IP, design tools and reference flows. The
Company’s total managed capacity in 2008 exceeded 9 million 8-inch
equivalent wafers, including capacity from two advanced 12-inch - GigaFabs(TM),
four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned
subsidiaries, WaferTech and TSMC (China), and its joint venture fab, SSMC. TSMC
is the first foundry to provide 40nm production capabilities. Its corporate
headquarters are in Hsinchu, Taiwan. For more information about TSMC please
visit http://www.tsmc.com.


Wendy Matthews, +1-408-382-8030, wmatthews@tsmc.com, or Michael Kramer,
+886-3-563-6688, ext. 7126216, pdkramer@tsmc.com, both of TSMC